1. Field of the Invention
The present invention relates to a signal generating circuit and a method thereof, and particularly relates to a signal generating circuit and a method thereof, which can determine which part of a target signal is output according to a delay phase of the target signal.
2. Description of the Prior Art
In the prior art, a PLL (phase locked loop) is utilized to perform clock signals with different phases. For example, the PLL is utilized to provide an initial phase locked clock signal, and a plurality of delayed phase locked clock signals having phases different from which of the initial phase locked clock signal.
Frequency-dividing operation may needs to be performed to the clock signals generated by the phase locked clock signal, since different devices may need different operating frequency and different duty cycles. However, phase error may occurs between clock signals before frequency dividing and clock signals after frequency dividing since the frequency divider is only triggered by rising edges or falling edges of clock signals. Therefore, the delay for clock signals should be selected based on phase differences for clock signals, to solve phase error between clock signals before frequency dividing and clock signals after frequency dividing.